Logic Rewiring for Delay and Power Minimization

Recent considerations in semiconductor portability and increasing clock cycle rates require designs that consume little power but meet strict performance requirements. Due to these facts, it becomes apparent that circuit optimization remains an important task in the overall design cycle. Traditionally, logic optimization is carried in two steps. In the first step, technology independent optimization is performed to produce an optimum design in terms of some general criteria such as gatecount or literal count. Symbolic-based techniques [8] have been very successful for this step. In the second step, technology dependent optimization is carried through an iterative sequence of successive design rewiring operations [1, 2, 4, 6, 7, 9, 10]. During each iteration of this procedure, a single target wire is identified for removal because it violates some specification constraints and some logic is added to eliminate the target wire. This process is repeated until the required optimization goals are achieved. In this work, we describe an application of the method by Veneris et al. [10] to multi-level combinational circuit technology dependent optimization. Unlike most rewiring techniques [1, 2, 4, 6, 7, 9] that eliminate a target wire by adding redundant logic, the method in [10] treats rewiring using a sequence of design error diagnosis and correction [11] steps. Under this perspective, the task of design rewiring is performed by intro-